Static random access memory device

专利摘要:
A static random access memory device according to the present invention comprises at least one pair of bit lines; At least one word line; At least one memory cell comprising two switch transistors, two latched pull-down transistors, and two load elements connected to the word line; A first power supply line extending in a bit line direction and connected with sources of the pull-down transistor; And a second power line extending in the same direction as the first power line and connected to bulk of the switch transistors and the pull-down transistors.
公开号:KR19990042164A
申请号:KR1019970062886
申请日:1997-11-25
公开日:1999-06-15
发明作者:모현선；김두응；곽충근
申请人:윤종용；삼성전자 주식회사；
IPC主号:

专利说明:

STATIC RANDOM ACCESS MEMORY DEVICE
The present invention relates to a semiconductor memory device, and more particularly, to a static random access memory device having a memory cell having a stress function.
Static random access memory (SRAM) is an example of two inverter flip-flops. These memory cells have a series of repeating array structures. As cell density increases, the reliability of weak cells also increases, which has a significant impact on product productivity.
In normal operation, an external power supply and ground potential were applied to the entire chip, which could not artificially "stress" only the integrated memory cells. In general, since the cell area where the micro process is performed has a very important influence on the stability of the chip and is very sensitive, there is a need for a method of testing the stability and reliability of the cell.
1 is a circuit diagram showing a SRAM cell according to the prior art. As shown in Fig. 1, a conventional SRAM cell has a common power supply voltage VCC and a ground potential GND. In a conventional array configuration, the peripheral region and the memory cell array region are provided with the same power supply voltage and ground potential.
As a result, failure does not occur in the proper operating area, but under irregular stress conditions, weak cells cause functional failures. In general, artificially stress the chip to test the reliability of the product. In this case, screening weak cells with a strong initial stress is very important in determining the life time of the product.
Accordingly, it is an object of the present invention to provide a static random access memory device capable of artificially exerting strong stress on a memory cell from outside.
1 is a circuit diagram showing a memory cell of an SRAM device according to the prior art;
2 is a circuit diagram showing a memory cell of an SRAM device according to a preferred embodiment of the present invention;
3 is a cross-sectional view showing a well structure of a memory cell according to the present invention;
* Explanation of symbols on the main parts of the drawings
M1-M6, M10, M12, M14, M16, M18, M20: Transistor
WL: word line BL, BLB: bit line
(Configuration)
According to one aspect of the present invention for achieving the above object, in a static random access memory device having at least one memory cell, at least one pair of bit lines and at least one word line: Two switch transistors, two latched pull-down transistors, and two load elements connected to the word line; The sources of the pull-down transistors are connected to a first power line having a first voltage and the bulk of the switch transistors and the pull-down transistors are connected to a second power line having a second voltage; The pull-down transistors are formed in a pocket-well separated from the substrate.
In this embodiment, the first and second voltages are characterized by having different voltage levels.
In this embodiment, the first voltage is characterized by the same level of ground power provided to the peripheral circuit.
In this embodiment, the second voltage may apply an external voltage in the reliability test mode, and has the same level as the first voltage during normal operation.
According to another aspect of the present invention, there is provided an electronic device comprising: at least one pair of bit lines; At least one word line; At least one memory cell comprising two switch transistors, two latched pull-down transistors, and two load elements connected to the word line; A first power supply line extending in a bit line direction and connected with sources of the pull-down transistor; A second power supply line extending in the same direction as the first power supply line and connected to a bulk of the switch transistors and the pull-down transistors; The first and second power lines are applied with first and second voltages of different levels; The memory cell is formed in a pocket well separate from the substrate.
In this embodiment, the first voltage is characterized by the same level of ground power provided to the peripheral circuit.
In this embodiment, the second voltage may apply an external voltage in the reliability test mode, and has the same level as the first voltage during normal operation.
(Action)
By such a device, the source of the pull-down transistors of the memory cell can be separated from the substrate, so that a strong artificial stress can be applied to the cell, allowing a large amount of current to flow through the cell node.
Hereinafter, reference will be made in detail with reference to FIGS. 2 and 3 according to an embodiment of the present invention.
In the following description, specific details are set forth by way of example and in detail in order to provide a more thorough understanding of the present invention. However, for those of ordinary skill in the art, the present invention may be practiced only by the above description without these details.
2 is a circuit diagram illustrating a memory cell of an SRAM device according to a preferred embodiment of the present invention, and FIG. 3 is a cross-sectional view illustrating a well structure of a memory cell according to the present invention.
Referring to FIG. 2, an SRAM cell consists of two switch transistors M10 and M12, two pulldown transistors M16 and M20, and two pullup transistors M14 and M18. have. Gates of the switch transistors M10 and M12 are connected to a word line WL, the current paths of which are between nodes N1 and N2 and corresponding bit lines BL and BLB. It is formed in each. The current paths of the transistors M14 and M16 are sequentially formed in series between the supply voltage VCC and the ground potential GND, the gates of which are commonly connected to the node N2 as a single inverter. Works.
The current paths of the transistors M18 and M20 are sequentially formed in series between the power supply voltage VCC and the ground potential GND, the gates of which are commonly connected to the node N1 as one inverter. Works. Here, the bulk of the transistors M10, M12, M16, and M20 is supplied with an externally adjustable power source TGND through a power supply line different from the ground potential GND. The relevant operation for this is described in detail later.
The present invention provides a separate ground potential to apply artificial "stress" to many memory cells to screen weak memory cells prior to package. First, the entire memory chip is divided into a cell portion and a peripheral portion, which in most cases share the power supply voltage (VCC), the ground potential (GND), and the semiconductor substrate. However, in the present invention, the ground of the cell region is divided into a first power ground (GND) and a second power ground (TGND) in order to give an arbitrary "stress" only to the cell region. Therefore, the present invention implements a memory cell capable of flowing a large amount of current through the cell node by artificially stressing the cell by separating the substrates of the NMOS transistors M16 and M20 from the cell and the substrate.
The present invention separates and pad-bonds the NMOS transistor region of the cell, that is, the switch transistors M10 and M12 and the semiconductor substrate P-SUB of the pull-down transistors M16 and M2 to stress such a stress. . Here, as shown in FIG. 2, the source of the pull-down transistors M16 and M20 is the first power ground GND, which is an external ground, and the substrate of the NMOS transistors is separated by an N-well so that the second power source is separated. Ground it.
As shown in FIG. 3, when a negative voltage is applied to the substrate portion of the NMOS transistor region of the memory cell, the leakage current of the cell node and the semiconductor substrate is increased due to the potential difference between the cell node and the semiconductor substrate regardless of an external power supply voltage. Will increase. This principle can cause any stress on the cell node. According to the circuit configuration according to the present invention, the following effects can be obtained.
The cell node high level of the SRAM is "VCC-Vtn". This is the bit line voltage minus the threshold voltage (Vth) of the switch transistors M10 / M12. Vcc is not applied to the cell node. If the bit line voltage is lowered than Vcc by line load, the high level of the cell node will be applied lower. This is the limit of the external power supply voltage, no matter how high the external power supply voltage is, the cell node is lower than the external power supply voltage, and the stress is reduced in the cell compared to the surrounding area. According to the present invention, a negative voltage is applied by separating a semiconductor substrate from a region where NMOS transistors of a cell are formed and an equal or higher external power voltage to a cell node.
The cell node may have a burn-in effect. If the leakage current of the cell node to the semiconductor substrate is the same as the normal at the operating voltage but rapidly increases at the high voltage such as the burn-in voltage, the present invention is not limited to the condition that a certain high voltage cannot be applied due to the operation of the peripheral circuit. Weak cells can be screened by applying more than the external burn-in voltage to only the cell node without affecting the circuit.
Finally, a test method for screening weak cells at low power supply voltages, in which a negative voltage is randomly applied to the cell substrate when the power supply voltage of a peripheral circuit such as a data retention mode is a low power supply voltage that can operate. And may cause a data flip failure caused by a high level of state instability of the cell node at a low power supply voltage. For this reason, by separating the ground potential in the initial wafer state, the weak memory cells can be screened to improve product life time, yield and productivity.
In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely an example, and various changes and modifications can be made without departing from the spirit and scope of the present invention. Of course.
As described above, the weak memory cells can be extracted in the wafer state in advance by separating the ground potential so as to stress the memory cells externally, and as a result, the reliability and yield of the semiconductor memory device can be improved.

权利要求:
Claims (7)
[1" claim-type="Currently amended] A static random access memory device having at least one memory cell, at least a pair of bit lines, and at least one word line:
The memory cell consists of two switch transistors, two latched pull-down transistors and two load elements connected to the word line;
The sources of the pull-down transistors are connected to a first power line having a first voltage and the bulk of the switch transistors and the pull-down transistors are connected to a second power line having a second voltage; And wherein the pull-down transistors are formed in a pocket-well separate from the substrate.
[2" claim-type="Currently amended] The method of claim 1,
And the first and second voltages have different voltage levels.
[3" claim-type="Currently amended] The method of claim 2,
And wherein the first voltage is equal to a level of ground power provided to a peripheral circuit.
[4" claim-type="Currently amended] The method of claim 2,
And the second voltage may apply an external voltage in a reliability test mode, and has the same level as the first voltage during a normal operation.
[5" claim-type="Currently amended] At least a pair of bit lines;
At least one word line;
At least one memory cell comprising two switch transistors, two latched pull-down transistors, and two load elements connected to the word line;
A first power supply line extending in a bit line direction and connected with sources of the pull-down transistor;
A second power supply line extending in the same direction as the first power supply line and connected to a bulk of the switch transistors and the pull-down transistors;
The first and second power lines are applied with first and second voltages of different levels; And the memory cell is formed in a pocket well separated from the substrate.
[6" claim-type="Currently amended] The method of claim 5,
And wherein the first voltage is equal to a level of ground power provided to a peripheral circuit.
[7" claim-type="Currently amended] The method of claim 5,
And the second voltage may apply an external voltage in a reliability test mode, and has the same level as the first voltage during a normal operation.

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同族专利:

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引用文献:

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公开号 | 申请日 | 公开日 | 申请人 | 专利标题

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法律状态:
1997-11-25|Application filed by 윤종용, 삼성전자 주식회사

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1997-11-25|Priority to KR1019970062886A

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1999-06-15|Publication of KR19990042164A

优先权:

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申请号 | 申请日 | 专利标题

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KR1019970062886A|KR19990042164A|1997-11-25|1997-11-25|Static random access memory device|